View SC900A_8688816.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

www.semtech.com 1 power management SC900A programmable penta uldo with reset and i 2 c interface ? five ldo regulators in one package ? i 2 c interface with multiple device capability ? independent i 2 c enable/disable of ldos ? independent i 2 c control of output voltages ? low thermal impedance of 40c per watt ? 150mv dropout at 150ma ? input range from 2.7v to 5.5v ? programmable power good ag ? minimal number of external components ? over temperature protection ? small 4mm x 4mm 20-lead mlpq package ? small input/output lter capacitors ? programmable vout range - 1.45v to 3.00v for ldos a and b 1.75v to 3.30v for ldos c, d and e november 14, 2005 description features typical application circuit applications the SC900A is a highly integrated power management de- vice for low power portable applications. the device con- tains ve adjustable low-dropout linear regulators (ldos) with cmos pass-devices as well as a band-gap reference, i 2 c interface, and dacs to control the output voltages. many features of the SC900A are programmable through the i 2 c interface. these include the ability to independent- ly turn on any combination of the ve regulators. all ve of the ldo output voltages are programmable in 50mv steps from 1.45v to 3.00v for ldos a and b, and from 1.75v to 3.30v for ldos c, d and e. each ldo can have an active shutdown or nonactive shutdown program op- tion through the interface. there is also a reset monitor ag that is associated with ldoa. in addition, the device has a separate programmable power good monitor ag that activates when one or more ldos go out of regula- tion. the SC900A offers signi cant quiescent current and space savings to the system designer by sharing refer- ence and biasing among ve ldos. the small and ther- mally ef cient 20-lead mlpq package make it ideal for use in portable products where minimizing layout area is critical. ? palmtop/laptop computers ? personal digital assistants ? cellular telephones ? battery-powered equipment ? high ef ciency linear power supplies + keypad vin ina inb incd ine en ldopgd arst sda scl a0 gnd ldoe ldod ldoa ldob ldoc vref vasel dgnd SC900A 2.2uf 2.2uf 2.2uf 2.2uf 2.2uf 0.1uf 4.7uf vbat - baseband processor audio processing digital interface pa tcxo & synthesiser transmitter section receiver section lna camera processing ccd
2 ? 2005 semtech corp. www.semtech.com power management SC900A parameter symbol maximum units input supply voltage v in -0.3 to +7 v digital input voltage v dig -0.3 to vin +0.3 v operating ambient temperature range t a -40 to +85 c operating junction temperature range t j -40 to +125 c peak ir flow temperature t lead 260 c storage temperature t stg -60 to +150 c thermal impedance junction to ambient (1) ja 40 c/w esd protection level (2) esd 2 kv exceeding the speci cations below may result in permanent damage to the device or device malfunction. operation outside of the parameters speci ed in the electrical characteristics section is not implied. unless otherwise noted v in = 3.7v, t a = -40 to +85 c. typical values are at t a = +25 c. (1) calculated from package in still air, mounted to 3? x 4.5?, 4 layer fr4 pcb with thermal vias under the exposed pad as per jesd51 standards. (2) tested according to jedec standard jesd22-a114-b. electrical characteristics absolute maximum ratings parameter symbol conditions min typ max units general supply voltage v in all outputs < vin - dropout 2.7 5.5 v quiescent current shutdown i q-shutdown 10 a supply bypass capacitor c vcc per input pin 1 f digital inputs digital input voltage v il 0.4 v v ih 1.6 v digital input current i dig -0.2 0.2 a digital outputs digital output voltage (1) v ol i sink = 1.2ma, v 1.8v 2 10 %ldob v oh i source = 0.5ma, v 1.8v 90 98 %ldob referencing and biasing circuitry quiescent current reference i q-ref 25 a reference voltage v ref 1.227 v v ref start-up time i vref c vref = 100nf 15 ms v ref bypass capacitor c vref 0.1 f
3 ? 2005 semtech corp. www.semtech.com power management SC900A electrical characteristics (cont.) parameter symbol conditions min typ max units ldo regulators quiescent supply current i q all ldos active in default states 190 360 a quiescent supply current at start-up i qsup ldo a, b, c active in default states v out + 0.5v < v in < 5.5v 125 a current limit i lim 250 410 650 ma bypass capacitor c byp ceramic, low esr 2.2 f ldo regulator a (core supply) output voltage accuracy voa a 1.45v v out 3.00v v out + 0.2v v in 5.5v i out = 1ma, t a = 25c -3 +3 % output voltage accuracy at 2.80v (dac = 11011) voas a i out = 1ma -2 +2 % output voltage accuracy at 1.80v (dac = 00011) i out = 1ma, t a = 25c -3 +3 % output voltage accuracy at 2.80v (dac = 11011) v out + 0.5v v in 5.5v, i out = 200ma -3.5 +3.5 % maximum output current iomax a 200 ma default setting: on vo a-hi vasel - high 2.80 v vo a-lo vasel - low 1.80 v line regulation at 1.8v, 2.8v linereg a i out = 1ma, v out + 0.2v < v in < 5.5v 2.5 12 mv load regulation at 1.8v, 2.8v loadreg a 1ma < i out <200ma -3 -20 mv dropout voltage v da v out = 3.0v, i out = 200ma 200 250 mv power supply rejection ratio psrr a f = 10hz - 1khz, c byp = 0.1 f, i out = 50ma, 2.5v v out 3.0v 60 db output voltage noise (2) e n-a f = 10hz - 100khz, i out = 50ma, c vref = 0.1 f, c out = 2.2 f, 2.5v v out 3.0v 45 v rms ldo regulator b (digital i/o supply) output voltage accuracy voa b 1.45v v out 3.00v v out + 0.15v v in 5.5v i out = 1ma, t a = 25c -3 +3 % output voltage accuracy at 2.80v (dac = 11011) voas b i out = 1ma -2 +2 % v out + 0.5v v in 5.5v, i out = 150ma -3.5 +3.5 % maximum output current iomax b 150 ma
4 ? 2005 semtech corp. www.semtech.com power management SC900A electrical characteristics (cont.) parameter symbol conditions min typ max units ldo regulator b (digital i/o supply) (cont.) default setting: on vo b 2.80 mv line regulation at 2.8v linereg b i out = 1ma, v out + 0.15v < v in < 5.5v 2.5 12 mv load regulation at 2.8v loadreg b 1ma < i out <150ma -3 20 mv dropout voltage v db v out = 3.0v, i out = 150ma 150 190 mv power supply rejection ratio psrr b f = 10hz - 1khz, c byp = 0.1 f, i out = 50ma, 2.5v v out 3.0v 60 db output voltage noise (2) e n-b f = 10hz - 100khz, i out = 50ma, c vref = 0.1 f, c out = 2.2 f, 2.5v v out 3.0v 45 v rms ldo regulator c output voltage accuracy voa c 1.75v v out 3.30v v out + 0.15v v in 5.5v i out = 1ma, t a = 25c -3 +3 % output voltage accuracy at 2.90v (dac = 10111) voas c i out = 1ma -2 +2 % v out + 0.5v v in 5.5v, i out = 150ma -3.5 +3.5 % maximum output current iomax c 150 ma default setting: on vo c 2.90 v line regulation at 2.90v linereg c i out = 1ma, v out + 0.15v < v in < 5.5v 2.5 12 mv load regulation at 2.90v loadreg c 1ma < i out <150ma -3 -20 mv dropout voltage v dc v out = 3.3v, i out = 150ma 150 190 mv power supply rejection ratio psrr c f = 10hz - 1khz, c byp = 0.1 f, i out = 50ma, 2.5v v out 3.3v 60 db output voltage noise (2) e n-c f = 10hz - 100khz, i out = 50ma, c vref = 0.1 f, c out = 2.2 f, 2.5v v out 3.3v 55 v rms ldo regulator d output voltage accuracy voa d 1.75v v out 3.30v v out + 0.15v v in 5.5v i out = 1ma, t a = 25c -3 +3 % output voltage accuracy at 3.10v (dac = 10111) voas d i out = 1ma -2 +2 % v out + 0.5v v in 5.5v, i out = 150ma -3.5 +3.5 %
5 ? 2005 semtech corp. www.semtech.com power management SC900A electrical characteristics (cont.) parameter symbol conditions min typ max units ldo regulator d (cont.) maximum output current iomax d 150 ma default setting: off vo d 3.10 v line regulation at 3.10v linereg d i out = 1ma, v out + 0.15v < v in < 5.5v 2.5 12 mv load regulation at 3.10v loadreg d 1ma < i out <150ma -3 -20 mv dropout voltage v dd v out = 3.3v, i out = 150ma 150 190 mv power supply rejection ratio psrr d f = 10hz - 1khz, c byp = 0.1mf, i out = 50ma, 2.5v v out 3.3v 60 db output voltage noise (2) e n-d f = 10hz - 100khz, i out = 50ma, c vref = 0.1 f, c out = 2.2 f, 2.5v v out 3.3v 55 v rms ldo regulator e output voltage accuracy voa e 1.75v v out 3.30v v out + 0.15v v in 5.5v i out = 1ma, t a = 25c -3 +3 % output voltage accuracy at 3.10v (dac = 10111) voas e i out = 1ma -2 +2 % v out + 0.5v v in 5.5v, i out = 150ma -3.5 +3.5 % maximum output current iomax e 150 ma default setting: off vo e 3.10 v line regulation at 3.10v linereg e i out = 1ma, v out + 0.15v < v in < 5.5v 2.5 12 mv load regulation at 3.10v loadreg e 1ma < i out = 150ma -3 -20 mv dropout voltage v de v out = 3.3v, i out = 150ma 150 190 mv power supply rejection ratio psrr e f = 10hz - 1khz, c byp = 0.1 f, i out = 50ma, 2.5v v out 3.3v 60 db output voltage noise (2) e n-e f = 10hz - 100khz, i out = 50ma, c vref = 0.1 f, c out = 2.2 f, 2.5v v out 3.3v 55 v rms a reset reset threshold reset thld 77 % reset active timeout delay t rd delay in default state 75 100 125 ms ldo power good pgood threshold pgood thld 77 % pgood active timeout delay t pg delay in default state 75 100 125 ms notes: 1) digital outputs are powered from ldob, so ldob must be active for operation of ldopgd and arst. 2) below 2.5v: becomes digital regulator.
6 ? 2005 semtech corp. www.semtech.com power management SC900A electrical characteristics (cont.) parameter symbol conditions min typ max units i 2 c interface interface complies with slave mode i 2 c interface as described by philips i 2 c speci cation version dated january 2000. digital input voltage v il 0.4 v v ih 1.6 v sda output low level i din (sda) = 3ma 0.4 v i din (sda) = 6ma 0.6 v digital input current i dg -0.2 0.2 a i/o pin capacitance c in 10 pf i 2 c timing clock frequency f scl 400 440 khz scl low period t low 1.3 s scl high period t high 0.6 s data hold time t hd_dat 0 s data setuptime t su_dat 100 s setup time for repeated start condition t su_sta 0.6 s hold time for repeated start condition t hd_sta 0.6 s setup time for stop condition t su_sto 0.6 s bus-free time between stop and start t buf 1.3 s
7 ? 2005 semtech corp. www.semtech.com power management SC900A device package SC900Amltrt (1)(2) mlpq20l SC900Aevb evaluation board notes: (1) available in tape and reel only. a reel contains 3,000 devices. (2) available in lead-free package only. device is weee and rohs compliant. pin con guration ordering information top view 1 2 3 4 12 11 10 9 16 15 14 13 5 678 mlpq20: 4x4 20 lead 17 18 19 20 t ldob inb sda scl en vref gnd vin ine ldoe ldoa ina ldoc incd ldod arst ldopgd vasel dgnd a0
8 ? 2005 semtech corp. www.semtech.com power management SC900A pin descriptions pin# pin name pin function 1 ldob ldo b output. 2 inb input supply for the digital system logic and the ldo b pass transistor. 3 sda bidirectional open drain digital i/o pin. i 2 c serial data. 4 scl digital input. i 2 c serial clock. 5 en digital input. high to enable part. low to disable part (sleep mode). note i 2 c control is active only when part is enabled. 6 a0 one bit address for connecting two SC900A devices on to the system through the i 2 c interface. 7 dgnd digital ground. 8 vasel ldo a selection default voltage. tie this pin to ground for 1.8v or inb for 2.8v. 9 ldopgd digital output. state change indicates that one of four ldo output voltages (a, c, d or e) is out of spec. note, desired state of pin is programmable through the i 2 c interface. 10 arst digital output. state change indicates ldo a output voltage is out of spec. note, desired state of pin is programmable through the i 2 c interface. 11 vref bandgap reference output voltage. connect at least 0.1 f to ground (c vref 0.1 f). 12 gnd analog ground. 13 vin analog supply voltage. 14 ine input supply for the ldo e pass transistor. 15 ldoe ldo e output. 16 ldod ldo d output. 17 incd input supply for the ldo c and ldo d pass transistors. 18 ldoc ldo c output. 19 ina input supply for the ldo a pass transistor. 20 ldoa ldo a output. t thermal pad thermal pad for heatsinking purposes. connect to ground plane using multiple vias. not connected internally.
9 ? 2005 semtech corp. www.semtech.com power management SC900A block diagram i 2 c interface en vasel scl sda a0 dac cntl ldo cntl reset cntl vob ldoa ldob ldoc ldod ldoe vref dgnd gnd ine incd inb ina vin ldopgd arst a0 sda scl vasel en ldo ref dac input out en ldo ref dac input out en ldo ref dac input out en ldo ref dac input out en ldo ref dac input out en reference inb dacs cntl input en dac a dac b dac c dac d dac e reset/shdn control reset arst ldopgd inb vob 19 2 13 5 8 4 3 6 10 9 17 14 7 12 15 16 18 1 20 11
10 ? 2005 semtech corp. www.semtech.com power management SC900A applications information general description each of the ve low-dropout linear regulators (ldos) can be independently enabled or disabled and their output voltages can each be set by an independent dac. these controls can be accessed through the i 2 c serial port. there are ve 8-bit volatile registers in the SC900A; one for each ldo (registers a,b,c,d,e). in addition there is one common reset and power good control register and one on/off control register. the active shutdown circuitry can be accessed through each ldo register (refer to the section ?active shutdown? on page 11 for more informa- tion). at power-up, the register contents are reset to their de- fault values and the arst for ldo a has a default start-up delay of 100ms. at any time the part can be put into it?s lowest power state (shutdown) by pulling the en pin low. whenever the en pin is forced low, the previous settings are lost and the part requires reprogramming to return to the desired state. when en is pulled high, the device starts up in the default state. a detailed description of the protocol used to load the registers with data is described in the section entitled ?using the i 2 c interface? on page 14. vin and enable pin the v in supply must be 2.7v before the en pin can be asserted. this means that the en pin should not be tied to v in so that it does not reach a logic high level before the input supply reaches 2.7v. ldoa (core supply) ldoa is intended to be used as the core supply. it has an output current capability of 200ma and a dedicated reset signal arst. ina is the dedicated input supply for this regulator. ldob (digital i/o supply) inb supplies power for the internal i 2 c interface and other digital i/o functions, while ldob supplies power for arst and ldopgd output ports (see block diagram). there- fore it is imperative that ldob be operational to make use of arst and ldopgd. if ldob is turned off by the on/off control register, these output ports will not function. ldo reset control register: arst pin there are two functions that can be programmed, de n- ing the arst pin action: ? set the polarity of the reset signal ? set the reset clear delay time in milliseconds as soon as the ldoa output voltage falls below its pro- grammed value, the arst pin is asserted. the polarity of the arst pin can be set to active high or active low during a reset condition, by bit 6 of the ldo reset control reg- ister. once the error condition is resolved (output rises to the programmed value), a delay is initiated before the arst pin is cleared. the delay is programmable by bits 0-1 of the ldo reset control register. the default delay time is 100ms, and the delay can be programmed for 0, 50, 100, or 150ms. ldopgd pin there are three functions that can be programmed to de ne the ldopgd pin action: ? set which ldos are to be monitored for power good ? set the polarity of the power good signal ? set the power good delay time in milliseconds bits 4 and 5 of the ldo reset control register select which ldo or ldos are monitored. ldo c, d and e can be monitored independently or ldos a, c, d, and e can be monitored collectively. the polarity of the ldopgd pin can be set to active high or active low by bit 7 of the ldo reset control register. as soon as any of the selected ldo output voltages which are monitored falls within spec, the ldo power good (ldopgd) pin is asserted. once the ldo output power is stable (output rises to the programmed value), a delay is initiated before the ldopgd pin is set. the delay is programmable by bits 2 and 3 of the ldo re- set control register. the default delay is 100ms, and this delay can be programmed to 0, 50, 100, or 150ms.
11 ? 2005 semtech corp. www.semtech.com power management SC900A r/w 000100 pin a0 to gnd = 0 pin a0 to vin = 1 x device type identifier device address applications information (cont.) active shutdown the shutdown control bits determine how the on-chip ac- tive shutdown switches behave. each ldo register uses bit 5 of the ldo output voltage data byte to control the shutdown behavior. when the active shutdown bit is en- abled (set to 1), the capacitance on the ldo output will be discharged by an on-chip fet after the ldo is disabled. when the active shutdown bit is disabled (set to 0), the output capacitance on the ldo output is discharged by the load. the default active shutdown state for all ldos is on. on/off control register each individual ldo may be turned on or off by accessing the on/off control register. ldos are turned on by set- ting their respective on/off bit to 1. likewise, they can be turned off by setting the on/off bit to 0. this allows for on/off control with a single write command. if the enable (en) pin is high and data is written to the ldo voltage reg- isters, the ldo outputs will go to the voltage prescribed by the output voltage code bits (0-4). data will not be lost when toggling the on/off bit from 0 to 1. however, if the en pin is forced low, all circuitry in the device is disabled. all programmed information is lost when the enable bit is subsequently pulled high. vasel pin the vasel pin sets the default voltage of ldo a, the core supply. when this pin is set to v in , the default voltage is 2.80v. when this pin is set to gnd, the default voltage is 1.80v. the voltage can be changed from its default state after start up by writing to the ldo voltage code register. device addressing following a start condition, the master must output the address of the slave it is accessing. the most signi cant six bits of the slave are the device type identi er (id). for the SC900A this is xed at 000100[b]. the next signi - cant bit addresses a particular device. a system can have up to two SC900A devices on the bus. the two addresses are de ned by the state of the a0 input (see figure 1). figure 1 - slave address structure when the a0 pin is tied to gnd, device 1 has an address of 0 and the combination of device type id and address is 0x08h. when the a0 pin is tied to v in , device 2 has and address of 1 and the combination of device type id and address is 0x09h. the last bit of the slave address de nes the operation to be performed. when set to a one a read operation is se- lected; when set to a zero a write operation is selected. following a start condition, the SC900A monitors the sda line comparing the slave address being transmitted with its slave address (device type id and state of a0 input). upon a correct compare the SC900A outputs an acknowl- edge on the sda line. depending on the state of the r/w bit, the SC900A will execute a read or write operation. protection circuitry the SC900A provides protection circuitry that prevents the device from operating in an unspeci ed state. these include under voltage lockout protection, over-tempera- ture protection and short-circuit protection. under voltage lockout the SC900A provides an under voltage lockout (uvlo) circuit to protect the device from operating in an unknown state if the input voltage supply is too low. when the bat- tery voltage drops below the uvlo threshold, the ldos are disabled. as the battery voltage increases above the hysteresis level, the ldos are re-enabled into their previ- ous states, provided enable has remained high. if en- able goes low, the SC900A will shut down. over temperature protection the SC900A provides an internal over-temperature (ot) protection circuit that monitors the internal junction tem- perature. when the temperature exceeds the ot thresh- old, the ot protection disables all the ldo outputs. as the junction temperature drops below the hysteresis level the ot protection re-enables all the ldos in their previous states, provided enable has remained high. if enable goes low, the SC900A will shut down. short-circuit protection each ldo output has short-circuit protection. if a short is applied to any output, the output voltage will drop and the output current will be limited to the short circuit current until the short is removed.
12 ? 2005 semtech corp. www.semtech.com power management SC900A applications information (cont.) layout considerations layout is straightforward if you use the gerber les on page 21 as a reference. notice that the input voltage feed to the SC900A is on the bottom of the board and vias con- nect this voltage track to the top of the board and then to the SC900A itself. the input bypass can be one 4.7 f capacitor, two 3.3 f capacitors, three 2.2 f capacitors or ve 1 f capacitors. the determining factor is how much copper is available on the input voltage feed track and how much room is available. if the input voltage track is very thin, then use ve 1 f capacitors placed very close to the input pins of the SC900A. if the input track is fairly thick, then you can use a single 4.7 f capacitor at the be- ginning of the voltage feed track since a wider track has less inductance per inch. the SC900Aevb has ve 1 f capacitors, but these can be replaced with one 4.7 f in place of c1 and opens in place of c9, c14, c15, and c16 (see page 20 for details). register name register address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ldo a ldo b ldo c ldo d ldo e ldo reset control on/off control register 0x00 0x01 0x02 0x03 0x04 0x05 0x06 xx xxx ldopgd pin reset polarity bit arst pin reset polarity bit ldopgd monitor logic bits ldopgd delay bits ldo (a) reset delay bits on/off control ldo e on/off control ldo d on/off control ldo c on/off control ldo b on/off control ldo a active shutdown 1 = on 0 = off output voltage codes table a for ldos a & b table b for ldos c, d & e 101 1 1 1 0000 on on on on on off off off off off ldo reset control logic table (defaults are in bold) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 result result resu lt result result ldopgd pin polarity arst pin polarity ldopgd monitor logic ldopgd delay arst delay 1 0 1 0 1 0 00 0 00 0 0 00 0 0 1 11 1 11 1 1 11 1 high: power fail low: power good high: power good low: power fail high: power good low: reset high: reset low: power good ldos a, c, d & e good ldo e good ldo c good ldo d good 150ms 100ms 50ms 0ms 150ms 50ms 100ms 0ms ldo reset control logic table (defaults are in bold) note: digital outputs are powered from inb, additionally ldob must be on for operation of ldopgd and arst. r/w 000100 a0 x device type identifier device address SC900A slave address
13 ? 2005 semtech corp. www.semtech.com power management SC900A applications information (cont.) output voltage code bits: a 5-bit linear dac controls the output voltage of each ldo. the dac and error-amp gain are scaled so that the lsb size at the output is 50mv. output voltage can be set by writing the proper code to the desired ldo register. see table a for the bitcodes and their corresponding voltages for ldos a and b, and table b for the bitcodes and corresponding voltages for ldos c, d and e. bit 4 bit 3 bit 2 bit 1 bit 0 ldo output voltage 0 0 0 0 0 1.45v 0 0 0 0 1 1.50v 0 0 0 1 0 1.55v 0 0 0 1 1 1.60v 0 0 1 0 0 1.65v --- - - - --- - - - 1 1 1 1 0 2.95v 1 1 1 1 1 3.00v table a - ldo output voltage control settings for ldos a and b table b - ldo output voltage control settings for ldos c, d and e bit 4 bit 3 bit 2 bit 1 bit 0 ldo output voltage 0 0 0 0 0 1.75v 0 0 0 0 1 1.80v 0 0 0 1 0 1.85v 0 0 0 1 1 1.90v 0 0 1 0 0 1.95v ----- - ----- - 1 1 1 1 0 3.25v 1 1 1 1 1 3.30v
14 ? 2005 semtech corp. www.semtech.com power management SC900A using the i 2 c interface the SC900A is a read-write slave mode i 2 c device and complies with the philips i 2 c standard version 2.1 dated january 2000. the SC900A has six user-accessible internal 8-bit registers. the i 2 c interface has been designed for program exibility, in that once the slave address has been sent to the SC900A enabling it to be a slave transmitter/receiver, any register can be written to or read from independently of each other. while there is no auto increment/decrement capability in the SC900A i 2 c logic, a tight software loop can be designed to randomly access the next register indepen- dent of which register you have been accessing. the start and stop commands frame the datapacket and the repeat start condition is allowed if necessary. SC900A limitations to the i 2 c speci cations seven-bit addressing is required for communication with the SC900A; ten-bit addressing is not allowed. any general call address will be ignored by the SC900A. note that the SC900A is not cbus compatible. finally, the SC900A can operate in standard mode (100kbit/s) or fast mode (400kbit/s). supported formats direct format - write the simplest format for an i 2 c write is the direct format. after the start condition [s], the slave address is sent, followed by an eighth bit indicating a write. the SC900A i 2 c then acknowledges that it is being addressed, and the master re- sponds with an 8-bit data byte consisting of the register address. the slave acknowledges and the master sends the appropriate 8-bit data byte. once again the slave acknowledges and the master terminates the transfer with the stop condition [p]. slave address register address data s w a aap s: start condition slave address: 7 bit w: write = ?0? register address: 8 bit a: acknowledge (sent by slave) data: 8 bit p: stop condition i 2 c direct format - write combined format - read after the start condition [s], the slave address is sent, followed by an eighth bit indicating a write. the SC900A i 2 c then acknowledges that it is being addressed, and the master responds with an 8-bit data byte consisting of the reg- ister address. the slave acknowledges and the master sends the repeated start condition [sr]. once again the slave address is sent, followed by an eighth bit indicating a read. the slave responds with an acknowledge and the previ- ously addressed 8-bit data byte. the master then sends a non-acknowledge (nack). finally the master terminates the transfer with the stop condition [p]. slave address register address slave address data nack s w a a sr r a p s: start condition slave address: 7 bit w: write = ?0? register address: 8 bit r: read = ?1? data: 8 bit a: acknowledge (sent by slave) nack: non-acknowledge (sent by master) sr: repeated start condition p: stop condition i 2 c combined format - read applications information (cont.)
15 ? 2005 semtech corp. www.semtech.com power management SC900A applications information (cont.) stop separated reads another read format is available which is, in effect, an extension of the combined format read. this format allows a master to set up the register address pointer for a read and return to that slave some time later to read the data. after the start condition [s], the slave address is sent, followed by a write. the SC900A i 2 c then acknowledges that it is being addressed, and the master responds with the 8-bit register address. the master then sends a stop or restart condition, and may address another slave. some time later the master sends a start or restart condition, and a valid slave address is sent, followed by a read. the SC900A i 2 c then acknowledges and returns the data at thee register address location that had previously been set up. i 2 c stop separated format - read slave address register address slave address b data nack s w a a s/sr r a p p slave address a s s: start condition slave address: 7 bit w: write = ?0? register address: 8 bit r: read = ?1? data: 8 bit a: acknowledge (sent by slave) nack: non-acknowledge (sent by master) sr: repeated start condition p: stop condition register address setup access master addresses other slaves register read access
16 ? 2005 semtech corp. www.semtech.com power management SC900A timing diagrams arst and ldopgd timing ldo on/off control via the i 2 c interface ldo a: v outa v arst 90% v arst v th(a) v th(a) 10% v arst t rd ldo a, c, d & e: v out v ldopgd v th v th 90% v ldopgd 10% v ldopgd t pgd scl sda v ldon stop start stop 40us 300us
17 ? 2005 semtech corp. www.semtech.com power management SC900A timing diagrams (cont.) enable vref ldo a ldo b ldo c ldo d ldo e arst ldopgd 15ms 100ms 100ms 15ms 200us default start-up, shutdown timing diagram
18 ? 2005 semtech corp. www.semtech.com power management SC900A 0 25 50 75 100 125 150 175 200 0 25 50 75 100 125 150 175 200 0 25 50 75 100 125 150 175 200 0 25 50 75 100 125 150 -12 -10 -8 -6 -4 -2 0 0 25 50 75 100 125 150 175 200 -12 -10 -8 -6 -4 -2 0 0 25 50 75 100 125 150 0 2 4 6 8 10 12 2.7 3.2 3.7 4.2 4.7 5.2 5.7 0 2 4 6 8 10 12 2.7 3.2 3.7 4.2 4.7 5.2 5.7 t = -40 ? c t = -40 ? c t = -40 ? c t = -40 ? c t = -40 ? c t = -40 ? c t = 25 ? c t = 25 ? c t = 25 ? c t = 25 ? c t = 25 ? c t = 25 ? c t = 85 ? c t = 85 ? c t = 85 ? c t = 85 ? c t = 85 ? c t = 85 ? c typical characteristics dropout voltage (ldoa) dropout voltage (ldob-e) load regulation (ldoa) v in = 3.7v load regulation (ldob-e) v in = 3.7v load current (ma) load current (ma) load current (ma) load current (ma) input voltage (v) input voltage (v) dropout voltage (mv) dropout voltage (mv) output voltage variation (mv) output voltage variation (mv) output voltage variation (mv) output voltage variation (mv) line regulation (ldoa-b) load current = 1ma line regulation (ldoc-e) load current = 1ma
19 ? 2005 semtech corp. www.semtech.com power management SC900A 20 25 30 35 40 45 50 0 25 50 75 100 125 150 175 200 20 25 30 35 40 45 50 0 25 50 75 100 125 150 -80 -70 -60 -50 -40 -30 -20 -10 0 10 100 1000 10000 -80 -70 -60 -50 -40 -30 -20 -10 0 10 100 1000 10000 t = -40 ? c t = -40 ? c t = 25 ? c t = 25 ? c t = 85 ? c t = 85 ? c load transient (ldoa-e) v in = 3.7v, i o = 10ma to 150ma step line transient (ldoa-e) v in = 3.7v, i o = 150ma v in 1v/div v o 10mv/div v o 20mv/div i o 100ma/div 1ms/div 1ms/div output noise v load current (ldoa-b) vin = 3.7v, v o = 3v output noise v load current (ldoc-e) vin = 3.7v, v o = 3.3v psrr v frequency (ldoa-b) v in = 3.7v, v o = 3v psrr v frequency (ldoc-e) v in = 3.7v, v o = 3.3v load current (ma) load current (ma) frequency (hz) frequency (hz) power supply rejection (db) power supply rejection (db) output voltage noise ( v) output voltage noise ( v)
20 ? 2005 semtech corp. www.semtech.com power management SC900A evaluation board schematic vdd p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 gnd d- d+ vbus vregin p3.0/c2d c2ck/rst vin inb incd ine en ldopgd arst sda ina scl a0 gnd ldoa ldob ldoc ldod ldoe vref vasel dgnd 1 1 ldoa ldob ldoc ldod ldoe j1 j2 j3 j4 j5 c2 c3 c4 c5 c6 0.1uf 2.2uf 2.2uf 2.2uf 2.2uf vin ina inb incd ine ldopgd arst 13 19 2 17 14 5 9 10 3 4 6 12 20 1 18 16 15 11 8 7 vasel a0 tp5 tp6 SC900A pwr SC900A pwr 1 2 vasel j6 SC900A pwr enable tp9 r6 100k r9 100k SC900A pwr 100k 150 100k (non-use) r10 r11 SC900A pwr c10 0.1uf c7 2.2uf nc7s04 u3 1 2 3 4 5 sda scl tp3 tp4 tp8 tp7 tp1 tp2 am1 am2 7.5k 7.5k r5 r4 150 150 r1 r2 d1 d2 ldopgd arst fmmt3904 fmmt3904 q1 q2 7.5k r7 7.5k r8 c2dat c2clk program & debug j10 1 2 3 150 r16 d6 usb bus c13 1uf c12 4.7uf 150 r12 d4 external 150 r13 d5 usb 100k r14 100k r15 +5v usb c11 0.1uf c8 10uf j9 external supply +5v external sw1 SC900A pwr SC900A power select +5v usb 1 2 1 2 3 4 1a f1 j11 usb 6 1 32 31 30 29 28 27 26 25 24 23 22 21 20 19 2 18 17 16 15 14 13 12 11 10 9 7 8 5 4 3 r18 r17 0 gnd j7 gnd j8 c1 0.1uf c9 0.1uf c14 0.1uf c15 0.1uf c16 0.1uf vin ina inb incd ine SC900A pwr SC900A u1 u2 c8051f320 SC900A pwr r3 0 d3 enable
21 ? 2005 semtech corp. www.semtech.com power management SC900A evaluation board gerbers top gerber bottom gerber top silk gerber bottom silk gerber
22 ? 2005 semtech corp. www.semtech.com power management SC900A .001 max .002 - .040 nom 0.80 0.02 (0.20) 0.90 controlling dimensions are in millimeters (angles in degrees). coplanarity applies to the exposed pad as well as the terminals. notes: 2. 1. 1 2 n e1 .100 .106 .110 2.55 2.70 2.80 pin 1 indicator 4.10 3.90 4.00 4.10 3.90 .157 .153 .161 .153 .161 aaa c a c (laser mark) d e b a1 a a2 seating plane lxn e/2 bxn bbb c a b e d/2 d1 e1 inches .020 bsc b .007 bbb aaa n d1 e l e d .011 .100 dim a1 a2 a min .000 - .031 0.30 0.18 .012 0.25 .010 0.50 2.80 0.30 2.55 .004 .004 20 .016 .157 .106 .020 .110 0.10 0.10 20 0.40 4.00 2.70 0.50 bsc millimeters max 0.05 - 1.00 dimensions min 0.00 - nom (.008) .035 outline drawing - mlpq-20l 4 x 4 marking information top marking yy = two-digit year of manufacture ww = two-digit week of manufacture
23 ? 2005 semtech corp. www.semtech.com power management SC900A dimensions k h g z x p (c) company's manufacturing guidelines are met. 4.80 .189 z y this land pattern is for reference purposes only. consult your manufacturing group to ensure your notes: 1. dim x y h k p c g millimeters inches (3.95) .010 .033 .122 .021 .106 .106 (.155) 0.25 0.85 2.70 0.50 2.70 3.10 land pattern - mlpq-20l 4 x 4 semtech corporation power management products division 200 flynn road, camarillo, ca 93012 phone: (805) 498-2111 fax (805)498-3804 contact information

▲Up To Search▲

Price & Availability of SC900A

	To Download SC900A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .